- Industrial Sponsored VLSI Programs - For Top Semiconductor MNC's
- Career Counselling Sessions Every 2 Weeks To Discuss The Progress
- Real Industry Projects On Real Tools Led By Senior Industry Leaders
- English Language Evaluation & Feedback For Writing/Spoken Skills
- Trainer With 8+ Years Of Physical Design Experience
- Resume Building Session By Industry Experts
- 60 To 70% Of Course Time For Hands-on-Labs
- Learn By Doing Training Approach
- Regular Presentation Sessions
- 100% Placement Assistance
- Dedicated Mock Interviews
The Course Is Designed And Will Be Delivered By Experts In Physical Design, As Per The Industry Requirements. Importance Is Given To Cover The Concepts, Methodology With Good Emphasis On Hands-on Training, Using Industry Standard Tools With At Least 60 % Time Allocated To Lab Sessions With Quality Project At The End Of The Course.
Module 1: Linux, TCL, Perl• Shells• File And Directory Management• User Administration• Environment Variables• Commonly Used Commands• Shell Scripting Basics• SEd And AWK• Revision Management• Makefiles• Data Types, Variables, Assignments And Expressions• Lists, Arrays And Associative Arrays• Subroutines Or Procedures• Control Structures• File Input And Output• The World Of Regular Expressions• File Management
Module 2: CMOS Fundamentals• MOS Operation• I-V Characteristics Of MOS• Inverter Operation• Nand/Nor CMOS Circuits• MOS Second-order EffectsModule 3: Introduction To VLSI Flow• Specification• RTL Coding, Lint Checks• RTL Integration• Connectivity Checks• Functional Verification• Synthesis & STA• Gate Level Simulations• Power Aware Simulations• Placement And Routing• DFT• Custom Layout• Post Silicon ValidationModule 4: Initial Design Setup• Top Level, Sub-System Level And Block Level Design Setup• Set Up Initial Design Implementation• Loading Netlist From Synthesis• Setting Path To Dotlibs, LEFs, DEFs (if Needed), Technology Files, SDC Files• Flow Setup And Design Setup• Loop-back To Synthesis For Correlation Issues CorrectionModule 5: FloorPlanning• Initial FloorPlanning Settings• Define Pad Instances (Physical Cells)• Pad Instance Co-ordinates• Start FloorPlanning• Core Die Size Setting• FloorPlanning Of Pad Instances• Pad Filler Insertion• Define Pad Ring Power Grid• Macro Instance Constraints• Macro Instance Array Creation• Macro Instance Orientation• Anchor Based And Relative Placement Of Macro Instances• Macro Instance-Channel Settings• Macro Instance Placement - Manual• Congestion Probability Around Macro Instances• Defining Placement BlockagesModule 6: Placement• Running Placement• Defining Placement Strategies• In Place Optimization• Hierarchical Placement• Relative Placement• Congestion Analysis And Reduction• Macro Placement Changes To Reduce Congestion• Standard Cell Placement Constraints• Halo Creation For Instances• Congestion Analysis With Standard Cell Placement• Local Congestion Reduction• Density Screen And Placement Blockage For Standard Cells• Congestion Aware Placement• Re-Check Macro Placement For Better Congestion Relief• Create Balanced Buffer Trees For High Fanout NetModule 7: Power Planning• Defining Power Structure• Logical Power/Ground Connections• Setting Power Network Constraints• Create And Analyse Power Structure• Change Power Constraints And Re-Create To Meet IR Requirements• Power Ground Pin Connection And Create Power Rails• Power Network Checks For IR And Resistance• Placement Blockage For Power Network• Incremental PlacementModule 8: Scan Chain Re-Ordering And Re-Placement• Re-Order Scan Connectivity Within Chain• Re-Partition Scan Connectivity Across Chains• SCANDEF File-based Scan Chain Re-OrderingModule 9: Global Routing• Congestion Checks For Overflow Again• RC Extraction For Net Parasitics• Check Timing For Max Analysis• Run Timing/Congestion Aware Placement• Logic Re-Structuring For Placement And TimingModule 10: Clock Tree Synthesis (CTS)• Check Pre-CTS Timing Based On Global Routing And Detailed Placement• Setting Clock Constraints Such As Target Skew Target Insertion Delay• Clock Root Attributes As Stop, Float And Exclude Pins• Building For Generated And Gated Clocks• Don't Touch Attribute On Existing Clock Tree Structure• Defining Clock Buffers And Inverters.• Set Clock Tree Timing DRCs.• Non-Default Clock Routing Rules Setting• Perform Clock Tree Synthesis And Clock Tree Optimization• Reduce Hold Violations In Data Paths And Scan Paths• Clock Tree Building/Optimization For Multiple Modes And Multiple PVT Corners• Synchronous Clock Balancing• Cross-Clock Delay Balancing• Logical Hierarchy Aware CTS• Max And Min Analysis And Subsequent Optimization• Fixing Violations• CTS Optimization Across Other Modes And PVT Corners (MMMC)• Skew And Insertion Delay Checks• Checking Crosstalk On Clock NetworkModule 11: Detailed Routing• Pre-Route Check Points• Routing Fundamentals• Global Route• Detail Routing• Track Assignment And Route• Refining Detailed Route• Over The Macro Routing• Non-Preferred Routing Direction• Clock Net Routing• Initial Data Path Routing• Redundant VIA Insertion Setting• Post Detailed Route Optimization• Fixing DRC Violations• Post Detailed Route Delay Calculation Algorithms• Crosstalk Delay And Noise Analysis And FixModule 12: Power Analysis (Static And Dynamic)• Check Leakage Power Dissipation• VT Cell Swap For Power And Timing Trade-o• Analysing Dynamic Power Dissipation Based On GAF, SAIF, VCD• Reduce Dynamic Power• Meet Total Power TargetModule 13: Timing Analysis & Optimization• Basic Timing Checks (setup, Hold)• Understanding Timing Constraints (SDC)• Timing Corners• Timing Report Analysis• General Optimization Techniques• Typical Causes For Timing Violations And Strategies For Fixing The Same.Module 14: ECO Flow• What Is ECO• Types Of ECO• Timing & Functional ECO Prep• Rolling In The ECO• Performing The ECO Placement And Routing.Module 15: Design For Manufacturing• Antenna Rules And Fixes• Critical Area Analysis• Wire Spreading And Widening• Setting Minimum Metal Jog Length• Filler Cell Insertion• Metal Fill• Timing Checks After Metal Fill• Parasitic Extraction For SignO• timing Analysis• Export Netlist• Export GDSIIModule 16: Sign-off Checks• Physical Verification (DRC, LVS, ERC)• IR Drop Analysis• Electro-Migration Analysis• Cross-Talk (SI) Analysis• Sign-off Timing Analysis• Logical Equivalence Checking
The Trainer Is Working As Lead Physical Design Engineer With A Leading VLSI Company Having 8+ Years Of Physical Design Experience In VLSI Industry, With Multiple Complex Tape Outs To His Credit.
He Is Passionate About Teaching And Mentored Many Entry / Mid Level Engineers Throughout His Corporate Career. He Is Excellent Trainer And Has Received Good Credentials For All His Training Deliveries. He Is Dynamic In Nature And Brings High Energy Levels To The Class.
He Teaches From His Rich Industry Experience, With Case Studies Of Various Design Problems He Has Faced While Working As PD Engineer.
The biggest certificate will be your dream job besides industry acknowledged and accepted "Certificate Of Excellence" in "Physical Design" using "Learn By Doing".
You need just 3 things to kick start your career with top semiconductor companies.
1. Industry acceptable practical technical know-how
2. Ability to present your self in front of top hiring companies in effective manner
3. Interview opportunity with Hiring Companies
Silicon Play is based at the industrial hub of bangalore for providing The Best Learning To Fresh Engineers. Engineers can expect the following unique and best practices at Silicon Play. Besides this Silicon Play has unique industry expert trainers where the Hiring Companies Pre-selects you at the beginning of the training program Itself.Silicon Play Has designed the courses to enable all these 3 most important aspects of Getting-you-Placed with Industry. Equal emphasis will be given to make you a good presenter.
Silicon Play has a objective to provide 100% Placements to all registered students.