- Industrial Sponsored VLSI Programs - For Top Semiconductor MNC's
- Career Counselling Sessions Every 2 Weeks To Discuss The Progress
- Real Industry Projects On Real Tools Led By Senior Industry Leaders
- English Language Evaluation & Feedback For Writing/Spoken Skills
- Trainer With 8+ Years Of Physical Design Experience
- Resume Building Session By Industry Experts
- 60 To 70% Of Course Time For Hands-on-Labs
- Learn By Doing Training Approach
- Regular Presentation Sessions
- 100% Placement Assistance
- Dedicated Mock Interviews
In Today’s Era, Complex SoC Chips Are Being Realized Using Complex VLSI(EDA) Tools, Of Which RTL2GDSII Flow Is Being Used Extensively During Any SoC Manufacturing. This Has Enabled The Realization Of Very Complex Digital Designs, Which Starts With Design Specification And Modeling Of Design Using HDL Language. This High Level Description Of Design Is Mapped To Its Corresponding Hardware Using Automation, Known As “Synthesis”, Without Which It’s Near To Impossible To Design Very Complex Digital Circuits.
In Order To Verify The Generated Hardware With The Original HDL Description, The Designer Can Choose Functional Verification Using Test-cases, But That Is Not Very Exhaustive. Hence There Is Need For Other Methodology Which Can Effectively Verify The Design Equivalence. This Is Achieved By Formal Verification, Also Known As Logical Equivalence Checking (LEC).
Timing(Frequency) Is One Of The Key Performance Metrics Of A Chip Along With Power And Area. Timing Closure Is The Major Milestone Which Dictates When A Chip Can Be Released (Tape-out) To The Semiconductor Foundry For Fabrication. Timing Closure Is A Specialized Skill For VLSI Engineers Working On RTL Design, Synthesis And Physical Design. Knowledge Of Timing Is Also Essential For Most Of The Engineers Working On ASIC Flow.
The Course Will Be Delivered By A Senior VLSI Engineer, Who Has Worked On Multiple Tape-outs For Synthesis, Timing Closure, Physical Design And LEC. Importance Is Given To Cover The Concepts And Methodology Thoroughly With Good Emphasis On Hands-on Training Using Industry Standard Tool Set, With At Least 50 % Of The Time Allocated To Lab Sessions.
This Course Offers Integrated Learning For Synthesis, Equivalence Checking & Sign-off STA Under One Umbrella Using Industry Standard EDA Tools. It Not Only Covers The Tool Aspects But Also Provides In-depth Technical Knowledge.
The biggest certificate will be your dream job besides industry acknowledged and accepted "Certificate Of Excellence" in "Physical Design" using "Learn By Doing".
50% Of The Time Is Allocated For Labs. Each Lecture Session Will Be Followed By Hands On Lab Session.
The Trainer Is Working With A Leading Product Semiconductor Company (MNC) , Handling Sign-off STA And PD.
He Has A Total Of 8+ Years Of Industry Experience. He Has Worked On Multiple Tape Outs, With Working Silicon.
His Area Of Expertise Includes Sign-off Timing Analysis And Physical Design. And Has Good Hands On Experience On RTL To GDSII Flow, Starting From RTL Design To Synthesis, DFT.