- Industrial Sponsored VLSI Programs - For Top Semiconductor MNC's

- Career Counselling Sessions Every 2 Weeks To Discuss The Progress

- Real Industry Projects On Real Tools Led By Senior Industry Leaders

- English Language Evaluation & Feedback For Writing/Spoken Skills

- Trainer With 8+ Years Of Physical Design Experience

- Resume Building Session By Industry Experts

- 60 To 70% Of Course Time For Hands-on-Labs

- Learn By Doing Training Approach

- Regular Presentation Sessions

- 100% Placement Assistance

- Dedicated Mock Interviews

  • Duration: 3 month/ 4 month
  • Timings:
    Weekdays: 08:00 AM to 08:00 PM
    Weekends: 08:00 AM to 08:00 PM
  • Start date: 2018-08-28 12:59:05

    Course Overview:

    In Today’s Era, Complex SoC Chips Are Being Realized Using Complex VLSI(EDA) Tools, Of Which RTL2GDSII Flow Is Being Used Extensively During Any SoC Manufacturing. This Has Enabled The Realization Of Very Complex Digital Designs, Which Starts With Design Specification And Modeling Of Design Using HDL Language. This High Level Description Of Design Is Mapped To Its Corresponding Hardware Using Automation, Known As “Synthesis”, Without Which It’s Near To Impossible To Design Very Complex Digital Circuits.

    In Order To Verify The Generated Hardware With The Original HDL Description, The Designer Can Choose Functional Verification Using Test-cases, But That Is Not Very Exhaustive. Hence There Is Need For Other Methodology Which Can Effectively Verify The Design Equivalence. This Is Achieved By Formal Verification, Also Known As Logical Equivalence Checking (LEC).

    Timing(Frequency) Is One Of The Key Performance Metrics Of A Chip Along With Power And Area. Timing Closure Is The Major Milestone Which Dictates When A Chip Can Be Released (Tape-out) To The Semiconductor Foundry For Fabrication. Timing Closure Is A Specialized Skill For VLSI Engineers Working On RTL Design, Synthesis And Physical Design. Knowledge Of Timing Is Also Essential For Most Of The Engineers Working On ASIC Flow.

    The Course Will Be Delivered By A Senior VLSI Engineer, Who Has Worked On Multiple Tape-outs For Synthesis, Timing Closure, Physical Design And LEC. Importance Is Given To Cover The Concepts And Methodology Thoroughly With Good Emphasis On Hands-on Training Using Industry Standard Tool Set, With At Least 50 % Of The Time Allocated To Lab Sessions.

    Uniqueness Of This Course:

    This Course Offers Integrated Learning For Synthesis, Equivalence Checking & Sign-off STA Under One Umbrella Using Industry Standard EDA Tools. It Not Only Covers The Tool Aspects But Also Provides In-depth Technical Knowledge.

    What Do You Get Out Of This Course?

    • In Depth Know-how Of Using Design Compiler For Synthesizing The Design Modeled In Verilog Or VHDL
    • Logical Equivalence Check Between Golden & Implemented Design.
    • Timing Analysis And Timing Closure Of Pre-Layout(Synthesized) And Post-Layout Designs.

    What Opportunities Could Open Up For You?

    • RTL Design/Application/CAD Engineers Can Migrate To Synthesis/STA Engineer Roles Or Up-skill Themselves To Deliver Effectively In Their Current Roles.
    • FPGA Engineers Can Migrate To Synthesis/STA Engineer Roles.
    • By Acquiring Timing Closure Proficiency, PD Engineers Can Significantly Improve Turn Around Times Of Their Blocks/designs. This In Turn Will Help Save Valuable Working Hours As Well As Open Up New Growth Opportunities.

    Who Can Attend This Course:

    • RTL Design, FPGA Design, DFT As Well As Physical Design Engineers Who Want To Learn Synthesis & STA Thoroughly.
    • Synthesis, STA Engineers Who Want To Fill The Gaps In Their Understanding & Strengthen STA Knowledge To deliver Effectively In Current Role.
    • CAD / Methodology Engineers Or Application Engineers Who Come Across Synthesis &  STA In Their Work.
    • Any Working VLSI Engineer Seeking To Learn Synthesis & STA.
    • M.tech (VLSI) Students, Who Want To Learn Synthesis & STA.

    Name and brand always carries a big value. You have an opportunity to leverage from the hard work and brand value of the SiliconPlay founders. 

    The biggest certificate will be your dream job besides industry acknowledged and accepted "Certificate Of Excellence" in "Physical Design" using "Learn By Doing".

    • Selected few will be receiving the special recommendation on their linkedIn profile directly by the founders.
    • Trainee of month award will be given on meeting certain criteria set by company management.
    • Trainee of the batch award will be given to the best student of whole training program.

    Course Content Outline:

    50% Of The Time Is Allocated For Labs. Each Lecture Session Will Be Followed By Hands On Lab Session.

    Basics And Synthesis (3 Weeks) :
    Linux, TCL, Perl
    CMOS And Digital Basics
    Introduction To Synthesis.
    Reading RTL In HDL Form, Dotlibs, SDC
    Different Types Of RTL Constructs
    Analysing Dotlib Les
    Elaboration And Generic Synthesis
    Understanding DesignWare Components And Logical Operators
    Clock Gating Insertion For Reducing Dynamic Power Post CTS
    Creating List Of Dont_touch And Dont_use Cells
    Technology Mapped Synthesis And Optimization
    Scan Insertion Techniques
    Checking Design For Number Of Instances, Area Estimate
    Check Clock Reaching Clock Pins Of Flops, Unclocked Flops
    Time Borrowing Concepts For Latch-based Paths
    Leakage Variants Of Standard Cells LVT, RVT, HVT
    Constraints On Logical Hierarchy Boundaries
    Setting Max Transition, Max Capacitance, Max Fanout
    Push Down And Pull Up Timing Constraints
    Master Clocks And Generated Clocks In Design
    Estimating Uncertainty Values, Input And Output Delays In SDC
    False Path, Multi Cycle Path Exceptions.
    Disabling Timing Loops In Design
    Logical Equivalence Checking Fundamentals (Top Level And Hierarchical)
    Hand Off Database To PnR
    Low Power Synthesis Using UPF
    Understanding The UPF And Low Power Concepts
    Understanding Of Low Power Cells And Their Requirement
    Low Power Synthesis Using UPF File
    Formal Verification (Equivalence Check) (0.5 Weeks)
    Loading Reference & Implemented Design
    Understanding & Matching Compare Points
    Verifying Design & Interpreting Results
    Debugging Verification
    SignOff Static Timing Analysis (3.5 Weeks) :
    STA Overview & Concepts
    Clocking – Handling Clock Muxes, Clock Dividers
    Generated Clocks, Clocking Exceptions
    Fundamental Setup And Hold Timing Checks
    Timing Arcs Across Design Instances
    Stage Delay Covering Cell Delay And Net Delay
    Timing Exceptions
    Asynchronous Flop, Recovery And Removal Checks
    Cross Clock Timing Analysis
    Interface Timing Analysis (between Reg And IO)
    Clock Group-based Timing Analysis
    Crosstalk Delay And Crosstalk Noise
    Advanced On Chip Variation, CPPR
    Post Layout STA Using SPEF
    Multi-Mode Multi-Corner Timing Analysis
    Graph Based And Path Based Analysis
    Timing DRC – Transition, Capacitance, Fanout Fixes.
    Timing ECOs Generation, What-If Analysis
    Clock Path ECO And Data Path ECO
    Constraint Development Specifically Interface Timing

    Tools To Be Used:

    • Industry Standard Tools
    • Additional Lab Hours, To Enable You Spend More Time On Labs From Home. This Is On Top Of Trainer Led Lab Sessions On Weekends.


    • Course Completion Certificate From Silicon Play


    The Trainer  Is Working With A Leading Product Semiconductor Company (MNC) , Handling Sign-off STA And PD.

    He Has A Total Of 8+ Years Of Industry Experience. He Has Worked On Multiple Tape Outs, With Working Silicon.

    His Area Of  Expertise Includes Sign-off Timing Analysis And Physical Design. And Has Good Hands On Experience On RTL To GDSII Flow, Starting From RTL Design To Synthesis, DFT.