- Industrial Sponsored VLSI Programs - For Top Semiconductor MNC's

- Career Counselling Sessions Every 2 Weeks To Discuss The Progress

- Real Industry Projects On Real Tools Led By Senior Industry Leaders

- English Language Evaluation & Feedback For Writing/Spoken Skills

- Trainer With 8+ Years Of Physical Design Experience

- Resume Building Session By Industry Experts

- 60 To 70% Of Course Time For Hands-on-Labs

- Learn By Doing Training Approach

- Regular Presentation Sessions

- 100% Placement Assistance

- Dedicated Mock Interviews

  • Duration: 3 month/ 4 month
  • Timings:
    Weekdays: 08:00 AM to 08:00 PM
    Weekends: 08:00 AM to 08:00 PM
  • Start date: 2018-08-28 18:18:00

    Course Overview:

    Design For Testability (DFT) Is A Specialization In The SOC Design Cycle, Which Facilitates A Design For Detecting Manufacturing Defects.  With Increase In Size & Complexity Of Chips, Facilitated By Advancement Of Manufacturing Technologies, It Has Evolved As A Specialization In Itself Over A Period Of Time.  DFT Engineers,  works On Introducing Various Test Structures As Part Of The Design Flow, To Increase The Testability Of Logic, Pads, Memories, Interconnects.

    This Course Is Designed For The Working VLSI / Electronics Engineers Who Want To Learn / Enhance Their Knowledge On Design For Testability (DFT) And Become Skilled DFT Engineers.

    The Course Is Designed And Will Be Delivered By Experts In DFT, As Per Current Project Requirements.  Importance Is Given To Cover The Concepts, Methodology Thoroughly With Good Emphasis On Hands-on Training, Using Industry Standard DFT Tools With At Least 50 % Time Allocated To Lab Sessions.

    Learning Outcome:

    At The End Of This Course, The Candidate Will Be Able To:

    • Read In The Netlist That Has DFT Logic Inserted In It And Along With The Various SPF Files In The ATPG EDA Tool.
    • Build The ATPG Model.
    • Run DRC Checks On The Design.
    • Generate Patterns For Stuck-at And At-speed Models.
    • Review Test Coverage & Do Incremental ATPG.
    • Write-out The Patterns.
    • Diagnose Failure Logs Provided By The ATE Engineer


    Who Can Attend This Course:

    • Entry Level / Experienced DFT Engineers, Who Want To Learn DFT In A Systematic Way From Fundamentals To Techniques, Methodologies.
    • RTL Design, Verification, Synthesis, STA And Physical Design Engineers, CAD Engineers Who Need To Understand DFT For Effective Integration Into Their Respective Design Flows.
    • Application Engineers Who Need To Understand DFT, For Effective Customer Interactions & Problem Solving
    • Faculty Working In Engineering Colleges, Teaching VLSI Subjects.
    • Anyone Interested To Learn Basic To Intermediate Level Of DFT Concepts And Tool Flow.
    • M.tech (VLSI) Interns/Freshers/Students

    Course Content Outline:

    Duration: 9 Weeks

    Each Module Has Associated Labs.  Theory Session Will Be Followed By Hands On Labs.

    Basics and SCAN/JTAG Insertion

    Week 1:

    • Linux, TCL, Perl
    • CMOS and Digital Basics
    • Full ASIC Flow – DFT
    • DFT Basics
    • Understanding Of SCAN In Depth
    • Scan Architecture Overview
    • Types Of Scan
    • Scan Golden Rules

    Week 2:

    • Understanding And Analysis Of DFT DRC
    • Multiple Clock Handling
    • DRC Fixing With Examples
    • Full Scan Insertion And Stitching Without Compression
    • Generate Test Protocol And Understanding

    Week 3:

    • Basics/Need Of Compression
    • Compression Techniques
    • Scan Insertion With Compression
    • On-chip Clocking For At-speed Testing

    Week 4:

    • Hierarchical Scan Design
    • Top-Down Scan Insertion
    • Boundary Scan Basics
    • Boundary Scan Cell Operation In Detail
    • JTAG Basics, Operation And State Machine

    ATPG & Simulations


    • ASIC Flow
    • DFT Overview
    • DFT Flow
    • Understanding Of Defects And Faults
    • Functional Test Vs Structural Test
    • ATPG
    • Understanding Of Silicon Testing From Tester To Gate Level
    • Fault Detection
    • Faults And Fault Collapsing
    • ATPG Algorithm

    Week 2:

    • Fault Models
    • Types Of Fault Models
    • Different Types Of ATPG
    • Stuckat Fault Model With An Example
    • Understanding Of ATPG Constraints
    • Understanding Of SPF
    • ATPG DRC Analysis [2-3 Live Examples]
    • ATPG For Stuckat Fault Model
    • Test Coverage Vs Fault Coverage

    Week 3:

    • Usage Of ATPG Graphical Schematic Viewer
    • Analyzing Feedback Paths
    • ATPG Pattern Simulation Flow
    • Stuckat Pattern Simulation And  failure Debugging
    • Analyzing ATPG Faults
    • Coverage Improvement Techniques
    • ATPG Pattern Optimization

    Week 4:

    • At Speed Fault Models
    • Understanding Transition Fault ATPG
    • ATPG Setup For Transition Fault Model
    • ATPG For Transition Fault Model
    • Timing Exceptions In Atspeed Testing
    • Path Delay Fault Modelling
    • On-Chip Clock Controller

    Week 5:

    • Transition Pattern Simulation
    • Transition Pattern Simulation Failure Debugging
    • Introduction To Diagnosis
    • Diagnosis Flow
    • Analysing Failure Logs

    Tools To Be Used:

    • Industry Standard DFT Tool Set Will Be Used.
    • Additional Lab Hours, To Enable You Spend More Time On Labs From Home. This Is On Top Of Trainer Led Lab Sessions During Sundays.


    • Course Completion Certificate From Silicon Play.


    The Trainer Has 10+ Years Of VLSI  Industry Experience, With Last 8 Years Exclusively In DFT And Currently Working As DFT Lead For A Services Company. 

    He Is Passionate In Teaching & Sharing His Knowledge And Mentored Entry / Mid Level Engineers Throughout His Career.

    Name and brand always carries a big value. You have an opportunity to leverage from the hard work and brand value of the SiliconPlay founders. 

    The biggest certificate will be your dream job besides industry acknowledged and accepted "Certificate Of Excellence" in "Physical Design" using "Learn By Doing".

    • Selected few will be receiving the special recommendation on their linkedIn profile directly by the founders.
    • Trainee of month award will be given on meeting certain criteria set by company management.
    • Trainee of the batch award will be given to the best student of whole training program.